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Dan Kreiser

Dan kreiser

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Inhaltsverzeichnis

KUSZ

FPGA-Implementation:

Error sources:

We compare the output of BB1 and BB2.

BB1 receives a perfect SIGNAL and should alway receive the correct DATA. BB2 receives a distorted SIGNAL therefor errors can and will occur.

Synchronization Error

sync_error: sync_ok too early or too late

synchronization is correct when the sync_ok signal occurs at the same time or delayed by one clock_cycle

PHR Error

    Administrator: Dan Klann
    Mail: ortsbeirat@jaenickendorf.info

All descriptions and technical specifications are subject to change without any prior notice. © copyright 2014