Project_settings.tcl

Step 1

This file is the main setup and config file for the project. Here project specific changes must be done. This section describes all settings in detail to guide you through the setup of your project.

set project_directory

Step 2

Here the path to the current project must be written. No quotation marks are needed. Just write it down following this example:

/home/smith/project_folder

Step 3

Here the project name must be written. To avoid any problems project name should be the same as the top entity name. No quotation marks are needed.

set project_name

Step 4

set top_entity:

Here the name of the top entity must be written. This is the name of the top component as it is instanciated in the testbench or so. To avoid any problems top entity name and project name should be the same. No quotation marks are needed.

set clock_name:

Here the name of the clock pin of the top entity must be written. It is used by the simulation scripts to feed the design with a clock signal.

set clock_period:

Here the clock period used by the scripts is set. The written number is the clock period in nano seconds (ns).

set reset_name:

Here the name of the reset pin of the top entity must be written. It is used by the script to force reset signals to the design.

set source_file_vhdl{}:

Here all VHDL files of the used by the design must be listed except the files needed for simulation only. Be aware when writing into different lines that each line inside the brackets must be end by a „\“. Here is a simple example:

set source_file_vhdl{ \
    file1.vhd \
    file2.vhd \
    file3.vhd \
}

set source_file_verilog{}:

Here all Verilog files used by the design must be listed except the files needed for simulation only. Be aware when writing into different lines that each line inside the brackets must be end by a „\“. Here is a simple example:

set source_file_verilog{ \
    file1.v \
    file2.v \
    file3.v \
}

set tb_file_vhdl{}:

Here all VHDL testbench related files used by the design must be listed. Be aware when writing into different lines that each line inside the brackets must be end by a „\“. Here is a simple example:

set tb_file_vhdl { \
 util.vhd\
 sysdefs.vhd\
 tbestbench.vhd }

set tb_file_verilog{}:

Here all Verilog testbench related files used by the design must be listed. Be aware when writing into different lines that each line inside the brackets must be end by a „\“. Here is a simple example:

set tb_file_verilog { \
 util.v\
 sysdefs.v\
 tbestbench.v }

set tb_entity:

Here the name of the testbench entity must be written.

set architecture_name:

Here the name of the testbench architecture must be written. This can be helpful if a testbench contains of more then one architecture.

set project_simulation_time:

Here the runtime of the simulation is set. The specified value is in micro seconds (um)

set debug_simulation_mode:

If this parameter is set to '1' detailed information over all signal of the whole hierarchy is written into the Value Change Dump (VCD) File. If the parameter is set to '0' top entity information only is written into the VCD file. The information of the VCD file is important for power analysis.

set Value:

If this parameter is set to '1' the 250 nm value technology of the IHP is used for synthesis. If is set to '0' another technology must be choosen.

set SG13:

If this parameter is set to '1' the 130 nm technology of the IHP is used for synthesis. If is set to '0' another technology must be choosen.